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CS3301A
Low-noise, Programmable Gain, Differential Amplifier
Features & Desription
Signal Bandwidth: DC to 2 kHz Selectable Gain: x1, x2, x4, x8, x16, x32, x64 Differential Inputs, Differential Outputs
* * * * Multiplexed inputs: INA, INB, 800 termination Rough / fine outputs for CS5371A / 72A / 73A Max signal amplitude: 5 Vpp differential Low input bias: 1 nA typical
Description
The CS3301A is a low-noise differential input, differential output amplifier with programmable gain, optimized for amplifying signals from low-impedance sensors such as geophones. The gain settings are binary weighted (x1, x2, x4, x8, x16, x32, x64) and are selected using simple pin settings. Two sets of external inputs, INA and INB, simplify system design as inputs from a sensor and test DAC. An internal 800 termination can also be selected for noise tests. Amplifier noise performance is outstanding with a noise density of 8.5 nV/ Hz over the 0.1 Hz to 2 kHz bandwidth. Distortion performance is also extremely good, typically -121 dB THD at x1 gain. Flat noise down to 0.1 Hz and low total harmonic distortion make this amplifier ideal for low-frequency, low-amplitude, differential signals requiring maximum dynamic range.
ORDERING INFORMATION See page 15.
CLK VD
Outstanding Noise Performance
* 8.5 nV/ Hz from 0.1 Hz to 2 kHz * 0.180 Vp-p between 0.1 Hz and 10 Hz
Low Total Harmonic Distortion
* -121 dB THD typical (0.0000891%) * -112 dB THD maximum (0.0002512%)
Low Power Consumption
* Normal operation: 5.5 mA typical * Power down: 10 A typical
Small 24-pin SSOP Package Bipolar Power Supply Configuration
* VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
VA+ INA+ INB+
400
+ -
OUTR+ OUTF+
MUX0 MUX1
400
GAIN0 GAIN1 GAIN2
+
INAINBVA-
OUTFOUTR-
PWDN
GND
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2007 (All Rights Reserved)
MAR `07 DS757F1
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .............................................................................. 3 SPECIFIED OPERATING CONDITIONS ....................................................................................... 3 ABSOLUTE MAXIMUM RATINGS ................................................................................................. 3 TEMPERATURE CONDITIONS .................................................................................................... 3 ANALOG CHARACTERISTICS ..................................................................................................... 4 DIGITAL CHARACTERISTICS ...................................................................................................... 7 POWER SUPPLY CHARACTERISTICS ........................................................................................ 8 2. GENERAL DESCRIPTION ............................................................................................................. 9 2.1. Analog Signals .......................................................................................................................... 9 2.2.1. Analog Inputs................................................................................................................ 9 2.3.2. Analog Outputs ............................................................................................................. 9 2.4.3. Differential Signals...................................................................................................... 10 2.5. Digital Signals ......................................................................................................................... 10 2.6.1. Clock Input.................................................................................................................. 10 2.7.2. Gain Selection ............................................................................................................ 10 2.8.3. Mux Selection ............................................................................................................. 10 2.9.4. Power Down Selection................................................................................................ 11 2.10.Power Supplies ..................................................................................................................... 11 2.11.1. Analog Power Supplies............................................................................................... 11 2.12.2. Digital Power Supplies................................................................................................ 11 2.13.Connection Diagram.............................................................................................................. 12 3. PIN DESCRIPTION ....................................................................................................................... 13 4. PACKAGE DIMENSIONS ............................................................................................................. 14 5. ORDERING INFORMATION ........................................................................................................ 15 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................................. 15 7. REVISION HISTORY ................................................................................................................... 16
LIST OF FIGURES
Figure 1. CS3301A Noise Performance .......................................................................................... 4 Figure 2. Digital Input Rise and Fall Times ..................................................................................... 7 Figure 3. Multi-Channel System Architecture.................................................................................. 9 Figure 4. Single-Channel System Architecture ............................................................................. 10 Figure 5. CS3301A Amplifier Connections.................................................................................... 12 Figure 6. CS3301A Pin Assignments ............................................................................................ 13
LIST OF TABLES
Table 1. Digital Selections for Gain and Input Mux Control ............................................................ 7 Table 2. Pin Descriptions ............................................................................................................. 13
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1.
* * * *
CHARACTERISTICS AND SPECIFICATIONS
Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25C. GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half. Device is connected as shown in Figure 5 on page 12 unless otherwise noted.
SPECIFIED OPERATING CONDITIONS
Parameter Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Thermal Ambient Operating Temperature Industrial (-IS, -ISZ) TA -40 25 85 C 2% (Note 1) 2% (Note 2) 3% VA+ VAVD 2.45 -2.55 3.20 2.50 -2.50 3.30 2.55 -2.45 3.40 V V V Symbol Min Nom Max Unit
Notes: 1. VA- must be the most negative voltage to avoid potential SCR latch-up conditions. 2. VD must conform to Digital Supply Differential under Absolute Maximum Ratings.
ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies Positive Analog Negative Analog Digital [(VA+) - (VA-)] [(VD) - (VA-)] (Note 3) (Note 3) (Note 3) Symbol VA+ VAVD VADIFF VDDIFF IPWR IIN IOUT PD VINA VIND TSTG Min -0.5 -6.8 -0.5 (VA-) - 0.5 -0.5 -65 Max 6.8 0.5 6.8 6.8 6.8 50 10 25 500 (VA+) + 0.5 (VD) + 0.5 150 Parameter V V V V V mA mA mA mW V V C
Analog Supply Differential Digital Supply Differential Input Current, Power Supplies
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltages Digital Input Voltages Storage Temperature Range
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 3. Transient currents up to 100 mA will not cause SCR latch-up.
TEMPERATURE CONDITIONS
Parameter Ambient Operating Temperature Storage Temperature Range Allowable Junction Temperature Junction to Ambient Thermal Impedance Symbol TA TSTR TJCT JA Min -40 -65 -
Typ 65
Max 85 150 125
-
Unit C C C C / W
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ANALOG CHARACTERISTICS
CS3301A Parameter Noise Performance Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Distortion Performance Total Harmonic Distortion (Note 5) x1 x2 x4 x8 x16 x32 x64 x1 x2 x4 x8 x16 x32 x64 -121 -120 -120 -120 -120 -119 -116 0.0000891 0.0001000 0.0001000 0.0001000 0.0001000 0.0001122 0.0001585 -112 0.0002512 f0 = 0.1 Hz to 10 Hz f0 = 0.1 Hz to 2 kHz (Note 4) VNPP VND IND 0.18 8.5 100 0.40 12.0 Vp-p
nV/ Hz fA/ Hz
Symbol
Min
Typ
Max
Unit
THD
dB
Linearity (Note 5)
LIN
%
Notes: 4. Guaranteed by design and/or characterization. 5. Tested with a full scale input signal of 31.25 Hz.
CS3301A In-Band Noise
20 Noise Density (nV/rtHz)
Noise Density (nV/rtHz) 300 250 200 150 100 50 0
CS3301A Wide Band Noise
15
10
5
0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz)
0.1
1
10
100
1000
10000 100000 1E+06
Frequency (Hz)
Figure 1. CS3301A Noise Performance
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ANALOG CHARACTERISTICS (CONT.)
CS3301A Parameter Gain Gain, Differential Gain, Common Mode Gain Accuracy, Absolute Gain Accuracy, Relative (Note 6) (Note 7) (Note 8) 2x 4x 8x 16x 32x 64x Gain Drift Offset Offset Voltage, Input Referred Offset After Calibration, Absolute Offset Calibration Range Offset Voltage Drift (Note 10) OFST 5 1 100 0.1 15 V V % FS V / C (Note 11) OFSTCAL (Note 12) OFSTRNG (Note 4, 9) OFSTTC (Note 4, 9) GAINTC GAINREL GAIN GAINCM GAINABS x1 -0.4 x1 1 -0.2 -0.2 -0.2 -0.2 -0.3 -0.3 5 x64 2 0 ppm / C % % Symbol Min Typ Max Unit
6. Common mode signals pass unchanged through the differential amplifier architecture and are rejected by the CS5371A / 72A / 73A modulator CMRR. 7. Absolute gain accuracy tests the matching of x1 gain across multiple CS3301A devices. 8. Relative gain accuracy tests the tracking of x2, x4, x8, x16, x32, x64 gain relative to x1 gain on a single CS3301A device. 9. Specification is for the parameter over the specified temperature range and is for the CS3301A device only. It does not include the effects of external components. 10. Offset voltage is tested with the amplifier inputs connected to the internal 800 termination. 11. The absolute offset after calibration specification applies to the effective offset voltage of the CS3301A output when used with the CS5371A / 72A / 73A modulator and CS5376A / 78 digital filter, and is measured from the digitally calibrated output codes of the digital filter. 12. The CS3301A offset calibration is performed digitally with the CS5371A / 72A / 73A modulator and CS5376A / 78 digital filter and includes the full scale signal range. Calibration offsets of greater than 5% of full scale will begin to subtract from system dynamic range.
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ANALOG CHARACTERISTICS (CONT.)
CS3301A Parameter Analog Input Characteristics Input Signal Frequencies Input Voltage Range (Vcm Signal) Full Scale Input, Differential x1 x2 to x64 x1 x2 x4 x8 x16 x32 x64 BW VIN VINFS DC
(VA-)+0.7 (VA-)+0.7
Symbol
Min
Typ 1, 50 1 1 -130 120 40 0.24 -
Max 2000
(VA+)-1.25 (VA+)-1.75
Unit Hz V Vp-p Vp-p Vp-p mVp-p mVp-p mVp-p mVp-p G, pF M nA dB dB Vp-p V /C mA nF
95 (VA-)+0.5
5 2.5 1.25 625 312.5 156.25 78.125 2 5
(VA+)-0.5
Input Impedance, Differential Input Impedance, Common Mode Input Bias Current Crosstalk, Multiplexed Inputs Analog Output Characteristics Full Scale Output, Differential Output Voltage Range (Vcm Signal) Output Impedance Output Impedance Drift Output Current Load Capacitance (Note 14) (Note 14) (Note 4) Common to Differential Mode Rejection (Note 4, 7, 13)
ZINDIFF ZINCM IIN XT CDMR VOUT VRNG ZOUT ZTC IOUT CL
-
25 1
Notes: 13. Ratio of input common mode amplitude vs. output differential mode amplitude for a perfectly matched common mode input signal. Characterized with a 50 Hz, 500 mVpeak common mode sine wave applied to the analog inputs. 14. Output impedance characteristics are approximate and can vary up to 30% depending on process parameters.
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DIGITAL CHARACTERISTICS
CS3301A Parameter Digital Characteristics High Level Input Drive Voltage Low Level Input Drive Voltage Input Leakage Current Digital Input Capacitance Rise Times, Digital Inputs Except CLK Fall Times, Digital Inputs Except CLK Master Clock Specifications Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter (In-Band or Aliased In-Band) Master Clock Jitter (Out-of-Band) (Note 16) fCLK fDTY tRISE tFALL JTRIB JTROB 2.0 40 2.048 2.2 60 25 25 300 1 MHz % ns ns ps ns (Note 15) (Note 15) VIH VIL IIN CIN tRISE tFALL 0.6*VD 0.0 1 9 VD 0.8 10 100 100 V V A pF ns ns Symbol Min Typ Max Unit
Notes: 15. Device is intended to be driven with CMOS logic levels. 16. When CLK is tied to GND, an internal oscillator provides a master clock at approximately 2 MHz. CLK should be driven for synchronous system operation.
t rise t fa ll 0 .9 * V D 0 .1 * V D
Figure 2. Digital Input Rise and Fall Times
Input Selection 800 termination INA only INB only INA + INB
MUX1 0 1 0 1
MUX0 0 0 1 1
Gain Selection x1 x2 x4 x8 x16 x32 x64 reserved
GAIN2 0 0 0 0 1 1 1 1
GAIN1 0 0 1 1 0 0 1 1
GAIN0 0 1 0 1 0 1 0 1
Table 1. Digital Selections for Gain and Input Mux Control
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POWER SUPPLY CHARACTERISTICS
CS3301A Parameter Power Supply Current, Normal Analog Power Supply Current Digital Power Supply Current Analog Power Supply Current Digital Power Supply Current Power Supply Rejection Power Supply Rejection Ratio (Note 4, 18) PSRR 100 120 dB (Note 17) (Note 17) (Note 17) (Note 17) IA ID IA ID 5.5 0.2 8 2 6.8 0.25 12 8 mA mA A A Symbol Min Typ Max Unit
Power Supply Current, Power Down (PWDN=1)
Notes: 17. All outputs unloaded. Analog inputs connected to the internal 800 termination. Digital inputs forced to VD or GND respectively. 18. Power supply rejection characterized with a 50 Hz, 400 mVp-p sine wave applied separately to each supply.
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2. GENERAL DESCRIPTION
architecture of a single channel acquisition system using a CS3301A, CS5373A, and CS5378. 2.1
2.1.1
The CS3301A is a low-noise chopper-stabilized CMOS differential input, differential output amplifier for precision analog signals between DC and 2 kHz. It has multiplexed inputs, rough / fine outputs and programmable gains of x1, x2, x4, x8, x16, x32, and x64. The amplifier's performance makes it ideal for low-frequency, high dynamic range applications requiring low distortion and minimal power consumption. It's optimized for use in acquisition systems designed around the CS5371A/72A single/dual modulators and the CS5376A quad digital filter or the CS5373A modulator and CS5378 digital filter. Figure 3 on page 9 shows the system architecture of a 4-channel acquisition system using four CS3301A, two CS5372A, one CS4373A, and one CS5376A. Figure 4 on page 10 shows the system
Analog Signals
Analog Inputs
The amplifier analog inputs are designed for differential sensors. Input multiplexing simplifies system connections by providing separate inputs for a sensor and test DAC (INA, INB) as well as an internal termination for noise tests. The MUX0, MUX1 digital pins determine which multiplexed input is connected to the amplifier.
2.1.2 Analog Outputs
The amplifier analog outputs are separated into rough charge / fine charge signals to easily connect to the CS5371A/72A/73A modulator inputs. Each differential output requires two series resistors and a differential capacitor to create the modulator antialias RC filter.
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP CS5371A CS5372A Modulator System Telemetry
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP
CS5376A
Controller or Configuration EEPROM
Digital Filter Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5371A CS5372A Modulator Communication Interface
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP
CS4373A
Switch Switch MUX MUX
Test DAC
Figure 3. Multi-Channel System Architecture
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CS5373A Differential Sensor CS3301A CS3302A M U X AMP Modulator CS5378
Controller or Configuration EEPROM
Digital Filter
System Telemetry Test DAC
Figure 4. Single-Channel System Architecture 2.1.3 Differential Signals
Analog signals into and out of the CS3301A are differential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full scale 5 Vpp differential signal centered on a -0.15 V common mode can have: SIG+ = -0.15 V + 1.25 V = 1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the reverse case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = 1.1 V SIG+ is -2.5 V relative to SIGThe total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation can be done for SIG- relative to SIG+. Note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds 1.1 V and never drops below -1.4 V on either half of the signal. By definition, differential voltages are to be measured with respect to the opposite half, not relative
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to ground. A multimeter differentially measuring between SIG+ and SIG- in this example would properly read 1.767 Vrms, or 5 Vpp. 2.2
2.2.1
Digital Signals
Clock Input
The clock signal is used by the chopperstabilization circuitry of the amplifier analog inputs. The CLK pin can be driven by an external clock source for synchronous operation, or CLK can be grounded to run from its own internally generated clock signal. The CLK pin is connected to a clock detect circuit which will disable the internal clock and use an external clock if one is supplied. If the internal clock signal is to be used, the CLK pin should be connected to GND.
2.2.2 Gain Selection
The CS3301A supports gain ranges of x1, x2, x4, x8, x16, x32, and x64. They are selected using the GAIN0, GAIN1, and GAIN2 pins as shown in Table 1 on page 7.
2.2.3 Mux Selection
The analog inputs to the amplifier are multiplexed, with external signals applied to the INA+, INA- or INB+, INB- pins. An internal termination is also available for noise tests. Input mux selection is
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made using the MUX0 and MUX1 pins as shown in Table 1 on page 7. Although a mux selection is provided to enable the INA and INB switches simultaneously, signal current should not be driven through them in this mode. The CS3301A mux switches will maintain good linearity only with minimal signal currents.
2.2.4 Power Down Selection
When using bipolar power supplies, the analog signal common mode voltage should be biased to 0 V. The analog power supplies are recommended to be bypassed to system ground using 0.1 F X7R type capacitors. The VA- supply is connected to the CMOS substrate and as such must remain the most negative applied voltage. It is recommended to clamp the VA- supply to system ground using a reversed biased Schottky diode to prevent possible damage related to mis-matched power supply initialization.
2.3.2 Digital Power Supplies
A power-down mode is available to shut down the amplifier when not in use. When enabled, all internal circuitry is disabled, the analog inputs and outputs go high-impedance, and the device enters a micro-power state. Power down mode is selected using the PWDN pin, which is active high. 2.3
2.3.1
Power Supplies
Analog Power Supplies
The digital voltage across the VD and GND pins is specified for a +3.3 V power supply. The digital power supply should be bypassed to system ground using a 0.01 F X7R type capacitor.
The analog power pins of the CS3301A are specified to run from bipolar 2.5 V power supplies.
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2.4 Connection Diagram Figure 5 on page 12 shows a connection diagram for the CS3301A amplifier when used with the CS5372A dual modulator, the CS4373A Test DAC, and the CS5376A digital filter. The diagram shows differential sensors and test DAC inputs, and analog outputs with anti-alias RC components; power supply connections including recommended bypassing; and digital control connections back to the CS5376A GPIO pins.
3 2
GPIO (x3) GPIO (x2) GPIO MCLK PWDN CLK VD VA+
0.1F 0.01F
To CS5376A Digital Control
GAIN VA+ VA+
0.1F
MUX
VD
0.01F
VD CS3301A Differential Amplifier
VAVA0.1F
VA+ GND INAINBINB+ OUTROUTFOUTF+ OUTR+
680
VD MDATA1 MFLAG1 PWDN1
INA+
INR+ INF+
680 680 0.02F C0G 0.02F C0G
Differential Sensor
INFINR680
MCLK MSYNC
VREF+ CS4373A Test DAC 2.5 V Reference VREFDifferential Sensor
680 680 680
CS5372A Modulator
INRINF0.02F C0G 0.02F C0G
OFST
INF+ INR+
680
INA+ VA+ VA+
0.1F
INA-
INB-
INB+
OUTR-
OUTF-
OUTF+
OUTR+ VD VD VA-
MDATA2 MFLAG2 PWDN2 GND
CS3301A Differential Amplifier VAGND GAIN MUX PWDN CLK
0.01F
VA0.1F
VA0.1F
2 3
MCLK GPIO GPIO (x2) GPIO (x3)
To CS5376A Digital Control
Figure 5. CS3301A Amplifier Connections
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3. PIN DESCRIPTION
Positive Analog Power Supply Negative Analog Rough Output Negative Analog Fine Output Negative Analog Power Supply Non-Inverting Input A Inverting Input A Inverting Input B Non-Inverting Input B Test Mode Output Positive Analog Fine Output Positive Analog Rough Output Test Mode Select
VA+ OUTROUTFVAINA+ INAINBINB+ TESTOUT OUTF+ OUTR+ TEST0
1 2 3
4
24 23 22
21
MUX0 MUX1 GAIN0 GAIN1 GAIN2 PWDN GND TEST1 VD GND TEST2 CLK
Input Mux Select Input Mux Select Gain Range Select Gain Range Select Gain Range Select Power Down Mode Enable Ground Test Mode Select Positive Digital Power Supply Ground Test Mode Select Clock Input
5 6
7
20 19
18
8 9 10 11 12
17 16 15 14 13
Figure 6. CS3301A Pin Assignments
Pin Name VA+ VAVD GND INA+, INAINB+, INBOUTR+, OUTROUTF+, OUTFGAIN0, GAIN1, GAIN2 CLK PWDN MUX0, MUX1 TEST0 TEST1, TEST2 TESTOUT
Pin #
I/O
Pin Description
1 4 16 15, 18 5, 6 8, 7 11, 2 10, 3 22, 21, 20 13 19 24, 23 12 17, 14 9
I I I I I I O O I I I I I I O
Positive analog supply voltage. Negative analog supply voltage. Positive digital supply voltage. Ground. Channel A differential analog inputs. Selected via MUX pins. Channel B differential analog inputs. Selected via MUX pins. Rough charge differential analog outputs. Fine charge differential analog outputs. Gain range select. See Gain Selection table in Digital Characteristics section. Master clock input. Connect to GND to use internal oscillator. Power down mode enable. Active high. Analog input select. See Input Selection table in Digital Characteristics section. Test mode select, factory use only. Connect to VA- during normal operation. Test mode select, factory use only. Connect to GND during normal operation. Test mode output, factory use only. No connect during normal operation. Table 2. Pin Descriptions
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4. PACKAGE DIMENSIONS 24 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 7.90 8.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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5. ORDERING INFORMATION
Model Temperature Package
CS3301A-IS CS3301A-ISZ (lead free)
-40 to +85 C
24-pin SSOP
6.
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C 260 C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days
CS3301A-IS CS3301A-ISZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
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7. REVISION HISTORY
Date FEB 2007 MAR 2007 Preliminary release. Updated to final for QPL (Quality Process Level). Changes PP1 F1
Revision
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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